Method of forming a nanostructure

ABSTRACT

A method of forming a discrete nanostructured element at one or more predetermined locations on a substrate is presented. The method includes forming a mask member over the substrate. A window is formed in the mask member at each of one or more locations at which it is required to form the nanostructured element thereby to expose a portion of a surface of the substrate. A portion of the substrate exposed by the window at the one or more locations is removed to form one or more recesses in the substrate. The method further includes forming a layer of a nanostructure medium over a surface of the recess and annealing the structure thereby to form the nanostructured element in each of the one or more recesses. The nanostructured element includes a portion of the nanostructure medium and has an external dimension along at least two substantially orthogonal directions of less than substantially 100 nm.

FIELD OF THE INVENTION

The present invention relates to a method of forming nanostructures.

DESCRIPTION OF THE RELATED ART

Nanostructures such as nanoparticles and nanowires may be formed on asubstrate by, for example, first forming them in an environment awayfrom a surface of a substrate and subsequently depositing them on thesubstrate as discrete entities. Alternatively, nanostructures may benucleated and grown directly on a substrate. Nanoparticles and nanowiresmay for example be nucleated on a surface directly from a vapour ofmaterial.

However, conventional processes are unable to form or have difficulty informing nanoparticles or nanowires at predetermined locations or formingordered arrays of nanoparticles or nanowires.

SUMMARY OF THE INVENTION

It is an object of the present invention to at least partly mitigate atleast one of the above-mentioned problems.

It is a further object of embodiments of the invention to provide amethod of forming a nanoparticle at a predetermined location on astructure.

In a first aspect of the invention there is provided a method of forminga discrete nanostructured element at one or more predetermined locationson a substrate comprising the steps of: forming a mask member over saidsubstrate; forming a window in said mask member at each of one or morelocations at which it is required to form said nanostructured elementthereby to expose a portion of a surface of said substrate; removing aportion of said substrate exposed by said window at said one or morelocations to form one or more recesses in said substrate; forming alayer of a nanostructure medium over a surface of said recess; andannealing said structure thereby to form said nanostructured element ineach of said one or more recesses, said nanostructured elementcomprising a portion of said nanostructure medium, said nanostructuredelement having an external dimension along at least two substantiallyorthogonal directions of less than substantially 100 nm.

In a second aspect of the invention there is provided a method offorming a nanoparticle at one or more predetermined locations on asubstrate comprising the steps of: forming a mask member over saidsubstrate; forming a window in said mask member at each of one or morelocations at which it is required to form said nanoparticle thereby toexpose a portion of a surface of said substrate; etching a portion ofsaid substrate exposed by said window at said one or more locations toform one or more recesses in said substrate; forming a layer of aparticle medium over a surface of said recess; and annealing saidstructure thereby to form said nanoparticle in each of said one or morerecesses, said nanoparticle comprising a portion of said particlemedium.

In a third aspect of the invention there is provided a method of forminga nanowire at one or more predetermined locations on a substratecomprising the steps of: forming a mask member over said substrate;forming an elongate window in said mask member at each of one or morelocations at which it is required to form said nanowire thereby toexpose a portion of a surface of said substrate; etching a portion ofsaid substrate exposed by said window at said one or more locations toform one or more grooves in said substrate; forming a layer of a wiremedium over a surface of said groove; and annealing said structurethereby to form said nanowire in each of said one or more grooves, saidnanowire comprising a portion of said particle medium.

Some embodiments of the invention have the feature that a nanostructuremay be formed at a predetermined location on a surface of a structure.In some embodiments an array of nanostructures is formed by this method.The method allows ordered arrays of nanostructures such as nanowires andnanoparticles to be fabricated having predetermined spacing and locationon a surface of a structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 5 show structures formed during a process of forming anordered array of nanoparticles on a substrate according to an embodimentof the invention in which a square-base pyramidal recess is formed inthe substrate.

FIGS. 6 and 7 show structures in which a square-base pyramidal recess isformed in a substrate at the end of a passageway extending into thesubstrate generally perpendicular to a surface of the substrate.

FIGS. 8 to 10 show structures formed during a process of forming anordered array of nanoparticles on a substrate according to an embodimentof the invention in which a recess is formed having a generally cubic orcuboid shape.

FIGS. 11 and 12 show structures according to an embodiment of theinvention having a generally hemispherical recess formed in a surface ofa substrate.

FIGS. 13 and 14 show structures formed according to an embodiment of theinvention during a process of forming an ordered array of nanowires on asubstrate.

FIG. 15 shows a structure formed according to an embodiment of theinvention having a plurality of nanoparticles formed along an apex of agroove formed in a substrate.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a cross-sectional schematic illustration of a structure 100formed during a process of forming an ordered array of nanoparticlesaccording to an embodiment of the present invention. The structure, asshown, comprises a substrate 102. The substrate, in one embodiment,comprises a semiconductor wafer, such as silicon. The substrate, forexample, is a p-type (100) substrate. Other types of substrates are alsouseful.

In one embodiment, a hard mask 110 is provided over the substrate. Thehard mask, for example, comprises silicon oxide. In one embodiment, thehard mask is formed by thermal oxidation, such as heating the substratein an oxygen atmosphere at about 900° C. The thickness of the hard maskis, for example, about 10 nm. Other types of hard mask material,deposition techniques, or thicknesses are also useful.

A sacrificial layer 115 is formed over the hard mask layer. Thesacrificial layer serves as a soft mask for patterning the hard mask. Inone embodiment, the sacrificial layer comprises photoresist. Varioustypes of photoresist, such as polymethyl methacrylate (PMMA), can beused. The photoresist can be deposited on the substrate by spin-coating.The thickness of the soft mask, for example, is about 100 nm. Otherthicknesses of the sacrificial layer are also useful. An antireflectivecoating (ARC) can be provided beneath the photoresist to improvelithographic resolution.

As shown, the sacrificial layer has been patterned by a lithographicprocess to form a plurality of windows 117 therein. The windows 117 areformed to expose portions of the layer of hard mask over each locationof the substrate 102 at which nanoparticles are formed. For purposes ofsimplifying the discussion, only one window is shown. The window 117,for example, comprises a square shape. Other window shapes are alsouseful.

In some embodiments, the windows are around 200 nm wide, but other sizesare also useful. For instance, in some embodiments the windows are fromaround 50 nm to around 1 micron wide.

Referring to FIG. 2, the hard mask is patterned, removing portionsexposed by the windows of the soft mask to form a plurality of windows112. The patterned hard mask exposes portions of the substrate 102.

In one embodiment, the hard mask is patterned using an isotropic etch,such as a wet etch. The wet etch can employ a first etch solutionhaving, for example, 0.1 weight percent buffered hydrofluoric acid (HF)in deionised water at room temperature. Other types of etch processes,such as anisotropic etch, including reactive ion etch (RIE), are alsouseful in patterning the hard mask.

The sacrificial layer 115 is then removed after the hard mask ispatterned. In one embodiment, the photoresist layer is removed by a wetetch. In a preferred embodiment, the photoresist layer is removed byexposing it to a second etch solution having, for example, 30 weightpercent potassium hydroxide (KOH) in deionised water at about roomtemperature.

In accordance with one embodiment of the invention, the second etchsolution also anisotropically etches the exposed portions of thesubstrate. In one embodiment, the substrate is patterned to form arecess 120 having walls 125 defining an inverted pyramid shape. Theinverted pyramid shape comprises, for example, an inverted square-basepyramid shape. In some embodiments, the walls correspond tocrystallographic planes of the substrate. In some embodiments the wallscorrespond to (111) planes. In some embodiments, walls are providedcorresponding to (110) planes. In some embodiments, walls are providedcorresponding to (100) planes or any other suitable crystallographicplane.

Other orientations of substrate are also useful in addition to (100)substrates such as (110) and (111) oriented substrates.

Other first etch and/or second etch solutions are also useful, as arerecesses having other shapes. Isotropic etch processes are useful insome embodiments of the invention.

As shown in FIG. 3, a device layer 130 is deposited on the substrate.The device layer lines the surface of the hard mask and the walls of therecess. The device layer, in one embodiment, serves as a particlemedium. The device layer, for example, comprises gold (Au) and may havea thickness of about 10 nm. Other types of device layers are alsouseful. For example, the device layer can include but is not limited toNi, Al, Co, Ti, other metallic materials, metal alloys, compoundsincluding semiconductor and metallic compounds, or a combinationthereof.

Other thicknesses of the layer of particle medium 130 are also useful.For example, in some embodiments the layer of particle medium 130 may beformed to have a thickness in the range of from around 5 nm to around 50nm. In some embodiments, the layer of particle medium 130 may be adiscontinuous layer rather than a continuous layer, for example, onlylining the walls or the recess.

The layer of particle medium 130 may be formed by physical vapourdeposition at a pressure of around 1×10⁻⁶ Torr but other pressures arealso useful. Other methods of deposition are also useful such aschemical vapour deposition or electroplating.

FIG. 4 shows the structure of FIG. 3 following a process of annealingthe structure to cause agglomeration (or ‘breaking up’) of the generallycontinuous layer of particle medium 130. Annealing of the structure maybe performed in a nitrogen ambient atmosphere at a temperature of fromaround 600° C. to around 1000° C. During the process of annealing, thelayer of particle medium 130 breaks up due to surface tension wherebynanoparticles of particle medium 130 are formed.

In the embodiment of FIG. 4 it can be seen that a particle 140 has beenformed at an intersection 129 of four walls 125 defining the recess 120in the substrate 102. The intersection 129 of the structure of FIG. 4 iscoincident with an apex of the square-base pyramid shape defined by thewalls 125.

Following the annealing process, remaining portions of the layer of maskmedium 110 may be removed by exposure of the substrate to a solutionhaving 10 weight percent buffered hydrofluoric acid (HF) in deionisedwater at room temperature. In some embodiments, the layer of mask medium110 may be removed before annealing the structure.

FIG. 5 shows the structure of FIG. 4 in plan view. As shown, an orderedarray of recesses in the form of four rows of five columns of recesses120 each with walls 125 defining a pyramidal shape have been formed, butother forms of array may be used instead. Other sizes of array are alsouseful. In some embodiments of the invention disordered arrays ofrecesses may be formed.

FIG. 6 shows a structure having a substrate 202 in which a recess 220has been formed. The recess 220 has non-parallel walls 225 defining apyramidal shape similar to that of the structure of FIG. 4 and FIG. 5,with the additional feature that the walls 225 are provided at one endof a channel 226 defined by a set of four generally parallel walls 227.In other words, the recess 220 is itself recessed below a surface of thesubstrate.

The channel 226 of the embodiment of FIG. 6 is substantially square incross-section. However, other cross-sectional shapes are also useful. Insome embodiments, the channel may be substantially rectangular incross-section, the recess 220 having a roof-shaped portion.

The length of the channel 226 (and hence the depth at which thenon-parallel walls 225 are formed) may be varied according to therequirements of a particular application.

As can be seen from FIG. 6, a plurality of intersections 228, 229between two or more non-coplanar surfaces at angles to one another ofless than 180° are present. For example, four intersections 228 of wallsare present between respective adjacent walls 227 of the channel 226 andwalls 225 of the recess 220. In some embodiments, these intersections228 provide preferential nucleation locations for the formation ofnanoparticles 240 of particle medium 130. Similarly, a singleintersection 229 between walls 225 of the recess 220 provides apreferential nucleation site for the formation of nanoparticles 240 insome embodiments of the invention.

In some embodiments of the invention, preferential nucleation occurs atthe intersections 228, 229 because a reduction in overall free energy ofthe structure can be obtained. This is at least in part due to areduction in surface tension that is obtained by certain particles whenan increased area of contact between a particle and one or more walls ofthe structure occurs.

In some embodiments, a reduction in surface tension is obtained when asize of an area of contact between a particle and a wall of thestructure is reduced. Consequently, in some embodiments of the inventionparticles form preferentially away from intersections 228, 229.

FIG. 7 is a plan view of the structure of FIG. 6 showing an array ofrecesses 220 formed in the substrate 202. A plurality of nanoparticles240 can be seen within each of the recesses 220 at locationscorresponding to the intersections 228, 229 described above. As can beseen, nanoparticles 240 may form at the intersections 228 or away fromthe intersections 228.

FIG. 8 shows an alternative structure to that of FIG. 2 following aprocess of etching the structure of FIG. 1 to form a recess 320 havingthe shape of a cuboid rather than the square-base pyramid of FIG. 2. Inthe embodiment of FIG. 8 the structure was formed by a reactive ionetching (RIE) process.

By cuboid it is meant a generally rectangular parallelepiped.

FIG. 9 shows the structure of FIG. 8 following a process of forming alayer of a particle medium 330 over the structure. In the embodiment ofFIG. 9, the particle medium may be gold (Au) and the layer may be formedby thermal evaporation, but other methods of depositing the particlemedium 330 are useful. Other materials are also useful such as thosedescribed above with respect to the embodiment of FIGS. 1 to 7.

It can be seen from FIG. 9 that the layer of particle medium 330 formsprimarily over lateral surfaces of the structure, i.e. over surfacesgenerally parallel to a plane of the substrate 102.

FIG. 10 shows the structure of FIG. 9 following a process of annealingthe structure to cause agglomeration of the layer of particle medium 330to form a plurality of nanoparticles 340. In the embodiment of FIG. 9,it can be seen that nanoparticles 340 have nucleated at non-coplanarintersections of surfaces, such as at intersections 328 of basal wall325 a and sidewalls 325.

Nanoparticles have also nucleated at locations of a basal wall 325 adistal any such intersections 328. In other words, nanoparticles 340have also nucleated at locations of a wall 325 a of a recess 320 awayfrom any intersection 328 of said wall 325 a with sidewalls 325 of therecess 320.

FIG. 11 is a cross-sectional view of a structure 400 formed by a methodaccording to an embodiment of the invention. In the embodiment of FIG.11, a mask medium 410 has been formed over a substrate 402 and anordered array of windows 412 formed in the mask medium 410. Windows 412have been formed in the mask medium 410 to expose a portion of thesurface of the substrate 402.

The structure has then been exposed to an etch process to form a recess420 having a rounded concave shape, for example corresponding to aportion of a sphere. In the structure of FIG. 11 the recess is formed byan isotropic wet etch process. Other etch processes are also useful.

Nanoparticles 440 have been formed in the recess by annealing a layer ofa particle medium formed over the structure in a similar manner to thatdescribed with respect to other embodiments of the invention.

FIG. 12 is a plan view of the structure of FIG. 11 following removal ofremaining portions of the mask medium 410.

While the figures have shown, for example, pyramidal, cuboid andspherical recesses, other shapes of recess are also useful. In someembodiments, some recesses may be formed to overlap one another at leastpartially.

FIG. 13 shows a structure 500 formed during a process of forming ananowire or a linear arrangement of a plurality of nanoparticlesaccording to an embodiment of the invention. The structure has asubstrate 502 in which a groove 520 having a v-shape cross-section hasbeen formed. Although the groove is described as having a v-shapecross-section, it is to be understood that an apex of the groove may berounded rather than angular. Furthermore, other cross-sectional shapesof groove are also useful.

The groove 520 is formed by opening an elongate window 512 in a maskmember 510 formed over the substrate 502 to expose a portion of asurface of the substrate 502. The mask member 510 and the window 512 inthe mask member 510 may be formed in a similar manner to the maskmembers and windows described above with respect to other embodiments ofthe invention.

Once the window 512 has been formed, etching of the exposed portion ofthe substrate is performed by exposing the substrate to an anisotropicetch process. In the embodiment of FIG. 13 the anisotropic etch processinvolves exposure of the substrate to an etch solution having, forexample, 30 weight percent potassium hydroxide (KOH) in deionised water.

A layer of a nanostructure medium may then be formed over the structureand the structure annealed to cause agglomeration of the layer ofnanostructure medium. FIG. 14 shows a structure following annealing ofthe nanostructure medium whereby nanowires 545 are formed along an apex529 of each groove 520.

For the present purposes, by nanowire is meant a discrete element havinga dimension along each of two orthogonal directions that is generallyless than or equal to around 100 nm. In some embodiments, nanowires areformed having dimensions along two generally orthogonal (x, y)directions of less than around 50 nm. In some embodiments, nanowires areformed having corresponding dimensions of less than around 10 nm. Ananowire may have a length along a third direction (z) mutuallyorthogonal to the (x, y) directions of at least 150 nm. In someembodiments, the length of the wire is at least 1 micron.

In the embodiment of FIG. 13, Au may be used as the wire medium wherebynanowires of Au may be formed. Other wire media are also usefulincluding metallic materials, metal alloys, and compounds includingsemiconductor and metallic compounds.

In some embodiments, annealing conditions similar to those describedabove with respect to particle media are used to form nanowires. It willbe appreciated that the size of the nanowires may be controlled at leastto some extent by control of the size and shape of the v-shaped groove320, the thickness of the layer of wire medium, the annealing time,annealing temperature and ambient conditions during annealing includinggaseous background pressure and composition of background gas.

Nanowires formed according to some embodiments of the invention may besubsequently reacted with one or more further materials in order to forma required nanowire material. In some embodiments, the nanowires may becaused to react with the substrate in order to form a required nanowirematerial.

FIG. 15 shows a structure formed upon annealing the layer ofnanostructure medium formed over the structure of FIG. 13 to form aplurality of nanoparticles 540 along an apex 529 of the groove 520,rather than a nanowire 545 (as shown in FIG. 14). In other words, a rowof discrete nanoparticles is formed along the apex of the groove 520.

Other shapes of the groove 520 are useful including curved grooves (e.g.in the form of a portion of a cylindrical or other concave roundedsurface), generally cuboid grooves or any other suitable shape.

Multiple grooves may be formed immediately adjacent one another. In someembodiments of the invention a serrated groove structure is formed. Bythe term serrated is included a structure in which a plurality ofgrooves are formed in parallel with one another, the plurality ofgrooves together having a generally saw-tooth shaped cross-section.

It will be appreciated that in some embodiments of the invention thelayer of particle medium or wire medium is initially formed to bediscontinuous and not continuous. In some embodiments, the layer may besubsequently annealed to form a plurality of nanoparticles or nanowires.For example, in the case of embodiments in which nanowires are formed, aplurality of discontinuous nanowires may be formed in any one groove520.

In some embodiments of the invention in which one or more nanoparticlesare formed at a predetermined location on a substrate the one or morenanoparticles may be subsequently used to form a further nanostructuresuch as a nanowire or a nanotube.

For example, in some embodiments the nanowire or nanotube so formed isused as a ‘seed’ nanostructure to catalyse the formation of a furthernanostructure such as a nanowire or nanotube by vapour-liquid-solid(VLS) growth or any other suitable growth technique.

For example, the nanowire or nanotube may be heated to form a furthernanowire, nanoparticle and/or other nanostructure and/or by reactionwith the substrate or with a gaseous medium.

In some embodiments, an Au nanoparticle on a silicon substrate is heatedto a temperature of around 530° C. in a flowing silane (SiH₄) atmospherein order to form a silicon nanowire by vapor-liquid-solid (VLS) growth.For details of VLS growth, see for example R. S. Wagner and W. C. Ellis,Appl. Phys. Lett., 4, page 89, 1964.

In some embodiments, the silicon nanowire is formed by exposing thestructure to a flow of a gas comprising 5% silane (SiH₄) diluted in H₂gas at a pressure of 850 mTorr and a flow rate of 400 sccm for 10minutes. The structure is held at a temperature of 530° C. duringexposure to the flow of gas.

In other embodiments the nanostructure is heated in the presence of avapour to form a further nanostructure such as a nanocage (e.g. aroundan existing nanoparticle) or a nanotube (e.g. nucleated/catalysed by anexisting nanoparticle). In some embodiments the structure may be exposedto a vapour bearing at least one selected from amongst a Group IIelement, a Group III element, a Group IV element, a Group V element anda Group VI element of the periodic table. In some embodiments thestructure is heated in the presence of a vapour comprising at least oneselected from amongst a carbon-bearing vapor, a nitrogen-bearing vaporand a boron-bearing vapor. For example, exposure of a nanoparticle of Coor other particle material to a carbon-bearing vapour can result in theformation of a carbon nanotube. If the size of the nanoparticle issufficiently small (e.g. in the range of from around 1 nm to around 10nm, preferably around 2 nm to around 5 nm) a single-walled nanotube maybe formed

In yet other embodiments, a seed nanoparticle formed according toembodiments of the invention is heated in the presence of a vapourbearing nitrogen and boron (e.g. borazine) to form a boron nitridenanostructure such as a boron nitride nanocage and/or a boron nitridenanowire and/or a boron nitride nanotube. In some embodiments, a seednanowire formed according to an embodiment of the invention is heated toform a boron nitride nanostructure. In some embodiments, thenanostructure so formed is a nanowire.

One or more nanocages may also be formed around other nanoparticlesformed according to one or more embodiments of the invention in order toform further nanostructured materials.

Reference to a ‘nanoparticle’ herein is intended to include reference toa particle having dimensions along each three mutually orthogonal (x, y,z) axes not exceeding substantially 100 nm.

Reference to a ‘discrete’ element is intended to mean reference to anelement that is not intimately bound to a matrix comprising the samematerial as which the element is composed. Thus, reference to a discretenanostructured element would not include reference to a grain of agenerally continuous thin film having a grain size of 100 nm or less.

It will be appreciated that grooves may be formed in a structure such asa substrate, the grooves having bends, kinks, jogs and/or otherlocations at which a longitudinal axis of the groove changes itsorientation relative to other portions of the groove.

It will be appreciated that grooves and other formations may be formedat different depths of the structure and that connections betweennanowires formed at different depths can be contemplated. In someembodiments of the invention grooves may be formed at an angle to theplane of the surface whereby nanowires may be formed that do not lie ina plane parallel to the plane of the substrate surface. Thus in someembodiments of the invention nanowires may be formed that connectelements provided at different depths of a structure.

Throughout the description and claims of this specification, the words“comprise” and “contain” and variations of the words, for example“comprising” and “comprises”, means “including but not limited to”, andis not intended to (and does not) exclude other moieties, additives,components, integers or steps.

Throughout the description and claims of this specification, thesingular encompasses the plural unless the context otherwise requires.In particular, where the indefinite article is used, the specificationis to be understood as contemplating plurality as well as singularity,unless the context requires otherwise.

Features, integers, characteristics, compounds, chemical moieties orgroups described in conjunction with a particular aspect, embodiment orexample of the invention are to be understood to be applicable to anyother aspect, embodiment or example described herein unless incompatibletherewith.

What is claimed is:
 1. A method of forming a discrete nanostructuredelement at one or more predetermined locations on a substratecomprising: forming a mask member over said substrate; forming a windowin said mask member to expose a portion of a surface of said substrateat each of the one or more locations where said nanostructured elementis to be formed; removing a portion of said substrate exposed by saidwindow at said one or more locations to form one or more recesses insaid substrate; forming a layer of a nanostructure medium over a surfaceof said recess and the mask member; and annealing the layer of thenanostructure medium to form said nanostructured element in each of saidone or more recesses, said nanostructured element comprising a portionof said nanostructure medium, said nanostructured element having anexternal dimension along at least two substantially orthogonaldirections less than or substantially equal to 100 nm; and removing themask member after annealing the layer of the nanostructure medium.
 2. Amethod as claimed in claim 1 wherein the step of forming said one ormore recesses comprises the step of etching said structure.
 3. A methodas claimed in claim 1 wherein the step of forming a recess in saidsubstrate comprises forming a recess having one or more walls defining abase shape corresponding to at least one selected from amongst a portionof a pyramidal structure, a portion of a square-base pyramidalstructure, a portion of a cube, a portion of a cuboid, a concave roundedsurface, a portion of a surface of a sphere, a portion of a surface of acylinder and a groove of substantially v-shaped or u-shapedcross-section.
 4. A method as claimed in claim 3 wherein at least one ofsaid walls of said base shape is generally defined by a crystal plane ofsaid substrate.
 5. A method as claimed in claim 3 wherein said recesscomprises a passageway having said base shape provided at a first end ofsaid passageway, a second end of the passageway opposite said first endhaving an opening at said surface of said substrate.
 6. A method asclaimed in claim 5 wherein said passageway has bends, kinks, jogs and/orother locations at which a longitudinal axis of said passageway changesits orientation relative to other portions of the passageway.
 7. Amethod as claimed in claim 1 wherein the nanostructured elementcomprises a nanoparticle.
 8. A method as claimed in claim 1 wherein saidrecess comprises an elongate groove.
 9. A method as claimed in claim 8wherein said groove has a portion having a substantially v-shaped oru-shaped cross-section, said nanostructured elements being providedalong an apex of said v-shaped or u-shaped portion of said groove.
 10. Amethod as claimed in claim 8 wherein the nanostructured elementcomprises a nanowire.
 11. A method as claimed in claim 1 wherein saidmask member comprises silicon oxide.
 12. A method as claimed in claim 1wherein said nanostructure medium comprises a catalyst material.
 13. Amethod as claimed in claim 1 wherein the nanostructured element isformed at an intersection of non-parallel walls of the recesses.
 14. Amethod as claimed in claim 1 wherein said nanostructure medium comprisesat least one selected from amongst Au, Ni, Al, Co and Ti.
 15. A methodas claimed in claim 1 further comprising the step of heating saidnanostructure thereby to form a further nanostructure.
 16. A method asclaimed in claim 15 wherein the step of heating said nanostructurecomprises the step of heating said nanostructure in the presence of avapor.
 17. A method as claimed in claim 16 wherein said vapour comprisesa vapor bearing at least one selected from amongst a Group II element, aGroup III element, a Group IV element, a Group V element and a Group VIelement of the periodic table.
 18. A method as claimed in claim 17wherein said vapor comprises at least one selected from amongst acarbon-bearing vapor, a nitrogen-bearing vapor and a boron-bearingvapor.
 19. A method as claimed in claim 1 wherein the step of formingthe nanostructure medium comprises the step of forming a generallycontinuous layer of said medium.
 20. A method as claimed in claim 1wherein the step of forming the layer of the nanostructure mediumcomprises lining the surface of the mask member and walls of therecesses without filling the recesses.
 21. A method of forming a devicecomprising: providing a substrate prepared with a recess, wherein thesubstrate comprises a mask member over a top surface of the substrate,and the mask member comprises a window which exposes the recess, whereinthe window is formed by mask and etch processes; lining a top surface ofthe mask member and walls of the recess with a layer of a nanostructuremedium without filling the recess; annealing the layer of thenanostructure medium to form a nanostructure in the recess wherein thenanostructure comprising a portion of the nanostructure medium; andremoving the mask member after annealing the layer of the nanostructuremedium.
 22. The method of claim 21 wherein the nanostructure is formedat an intersection of non-parallel walls of the recesses.
 23. A methodof forming a nanowire at one or more predetermined locations on asubstrate comprising the steps of: forming a mask member over saidsubstrate; forming an elongate window in said mask member to expose aportion of a surface of said substrate at each of the one or morelocations where said nanowire is to be formed; etching a portion of saidsubstrate exposed by said window at said one or more locations to formone or more grooves in said substrate; forming a layer of a wire mediumover a surface of said groove; and annealing the layer of the wiremedium thereby to form said nanowire in each of said one or more groovesalong a bottom area of each of the grooves, said nanowire comprising aportion of said wire medium.
 24. A method as claimed in claim 23 whereinsaid groove comprises a portion having a substantially v-shaped oru-shaped cross-section, said nanowire being formed along an apex of saidportion of said groove.